Part 1 of how to work with both the processing system (PS), and the FPGA (PL) within a Xilinx ZYNQ series SoC. Error: the "NANDgate" verilog file i wrote was supposed to be titled "ANDgate," but functionally was the same :p sorry for the goof Link for Part 2: https://youtu.be/AOy5l36DroY Thanks for watching!